This invention relates to a data-array processing system employing a memory system for storing the data-array.
In order to increase the speed of such a system, it may be considered appropriate to employ a plural number N of processors which can process data in parallel. In an application where all of the N processors always access the same address of the memory system in parallel, a substantial increase in speed would be obtained. However, to provide a flexible system, the processors also need to be able to access different addresses of the memory system. With conventional technology, this would be enabled by causing the N processors to access the memory system in sequence, and thus the memory accessing speed would be no greater than if a single processor were used.
The present invention is concerned with the problem of enabling N parallel processors to make parallel access to a common memory system for increased speed whilst also allowing the processors to access different addresses for increased flexibility.
In accordance with the present invention, each processor is selectable to supply its required address via an address bus to the memory system to access the memory system, and each non-selected processor is operable to determine whether it requires access to the address on the bus, and if so to access the memory system at the same time as the processor which supplied the address to the bus. Accordingly, the processors make parallel accesses to the memory system where they can, and sequential access where this is not possible.
In the preferred embodiment, in order to control access by the processors, there is preferably provided a controller which, in conjunction with the processors, is programmed so that:
(a) the controller selects one of the processors which requires access and enables it for access;
(b) the selected processor puts its required address on the bus;
(c) the non-selected processors compare their required addresses with the address on the bus and for each where there is a match that processor also accesses the memory; and
(d) the controller determines whether any processor still requires access, and if so, steps "a" to "d" are repeated.
In one arrangement of the above, prior to step "a", each processor which requires access to the memory system sets a respective "unsatisfied" flag of the controller and any processor which accesses the memory system resets its unsatisfied flag of the controller. In an alternative arrangement, which is preferred in the case where each processor is operable to access a series of addresses, prior to step "a" each processor which requires access to the memory system sets a respective "unsatisfied" flag of the controller and any processor which accesses the memory system maintains its unsatisfied flag set if it requires access to a further address in its series, or resets its unsatisfied flag if it has completed access to its series of addresses. This may have a disadvantage, in that some of the processors may race ahead of others through their series of accesses, and therefore in a preferred modification of the above each processor is operable to maintain a pointer indicative of the progress of accesses through its series of addresses, and the controller is operable to give priority of access to one of the processors which has progressed less through its series than another of the processors.
In the case where the memory system is addressable in "page mode ", that is to say where a first address component does not change between one addressing operation and the next, in order to take advantage of this feature, in the preferred embodiment any non-selected processor which requires access to the memory at an address having a first component but not a second component matching the first and second components of the address on the bus is given priority in a subsequent memory access over a processor which requires access to the memory system at an address having neither a first component nor a second component matching those of the address on the bus. Thus, the benefit of page-mode access is maximized. In the case also where a processor which has progressed least through its series of addresses is given priority, as described above, this priority is given lesser priority than the page-mode priority. In the case where a controller is employed as described above, the system is preferably arranged such that in step "c" if there is match between the first component of any non-selected processor's required address and the first component address on the bus, that non-selected processor sets a respective "part-satisfied" flag of the controller, and in a subsequent step "a" the controller gives priority of selection to an unsatisfied processor which has set its part-satisfied flag over an unsatisfied processor which has not set its part-satisfied flag.
In order to control sequencing of the processors, the controller is preferably operable to supply a sequence enable signal to a processor sequencer when all of the processors have become satisfied.
The invention is more particularly, but not exclusively, concerned with processing arrays of data elements in which the relative positions of the data-elements in the array are significant in addition to the values of the data elements, for example as in pixel or vector data-arrays. In this case, the memory system is preferably operable to provide parallel access to a group of N memory locations for a group of N contiguous data-elements upon addressing by a single address, and the N processors are preferably arranged so that when some or all of them are accessing the same address, they can access different memory locations in the accessed group. Accordingly, it is possible for (a) all of the N processors to access in parallel different memory locations in a single group, (b) some of the N processors to access in parallel one or more memory locations in one group and then for others of the processors to access in parallel one or more memory locations of a different group, and (c) all of the N processors to access sequentially memory locations in different groups.